The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2022
Filed:
Dec. 09, 2019
Intel Corporation, Santa Clara, CA (US);
Anand S. Murthy, Portland, OR (US);
Glenn A. Glass, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Ravi Pillarisetty, Portland, OR (US);
Niloy Mukherjee, Portland, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Roza Kotlyar, Portland, OR (US);
Willy Rachmady, Beaverton, OR (US);
Mark Y. Liu, West Linn, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.