The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2022
Filed:
Jun. 09, 2020
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Yasutoshi Okuno, Hsinchu, TW;
Cheng-Yi Peng, Taipei, TW;
Ziwei Fang, Hsinchu, TW;
I-Ming Chang, Hsinchu, TW;
Akira Mineji, Hsinchu, TW;
Yu-Ming Lin, Hsinchu, TW;
Meng-Hsuan Hsiao, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Abstract
A method of forming a semiconductor device including a fin field effect transistor (FinFET), the method includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer made of SiGeSnM2, wherein 0<a, 0<b, 0.01≤(a+b)≤0.1, 0.01≤y≤0.1, and M2 is P or As.