The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2022

Filed:

Sep. 25, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yung-Chi Chu, Kaohsiung, TW;

Hung-Jui Kuo, Hsinchu, TW;

Yu-Hsiang Hu, Hsinchu, TW;

Sih-Hao Liao, New Taipei, TW;

Tian Hu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/12 (2006.01); H01L 21/00 (2006.01); H01L 21/4763 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/58 (2006.01); H01L 21/56 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3192 (2013.01); H01L 21/56 (2013.01); H01L 23/3185 (2013.01); H01L 23/481 (2013.01); H01L 23/585 (2013.01); H01L 24/24 (2013.01); H01L 24/82 (2013.01); H01L 2224/24105 (2013.01); H01L 2224/24155 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/82101 (2013.01); H01L 2224/82106 (2013.01); H01L 2924/181 (2013.01);
Abstract

A semiconductor package includes a semiconductor die including a sensing component, an encapsulant extending along sidewalls of the semiconductor die, a through insulator via (TIV) and a dummy TIV penetrating through the encapsulant and disposed aside the semiconductor die, a patterned dielectric layer disposed on the encapsulant and exposing the sensing component of the semiconductor die, a conductive pattern disposed on the patterned dielectric layer and extending to be in contact with the TIV and the semiconductor die, and a first dummy conductive pattern disposed on the patterned dielectric layer and connected to the dummy TIV through an alignment opening of the first patterned dielectric layer. The semiconductor die is in a hollow region of the encapsulant, and a top width of the hollow region is greater than a width of the semiconductor die.


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