The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2022

Filed:

Oct. 22, 2015
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Daniel Pedone, Munich, DE;

Hans-Joachim Schulze, Taufkirchen, DE;

Rolf Gerlach, Starnberg, DE;

Christian Kasztelan, Munich, DE;

Anton Mauder, Kolbermoor, DE;

Hubert Rothleitner, Villach, AT;

Wolfgang Scholz, Olching, DE;

Philipp Seng, Munich, DE;

Peter Tuerkes, Unterhaching, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 29/739 (2006.01); H01L 29/866 (2006.01); H01L 21/8249 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0259 (2013.01); H01L 27/0255 (2013.01); H01L 27/0623 (2013.01); H01L 27/0629 (2013.01); H01L 29/7393 (2013.01); H01L 21/8249 (2013.01); H01L 29/866 (2013.01);
Abstract

A temperature protected power semiconductor device has a substrate which includes a power field effect transistor (FET) and a thermosensitive element. The power FET has a gate electrode connected to a gate, a drift region, and first and second terminals for a load current. The load current is controllable during operation by a voltage applied between the gate and the first terminal. The thermosensitive element has a first contact connected to one of the gate electrode and first terminal of the power FET, and a second contact connected to the other one of the gate electrode and first terminal. The thermosensitive element is located close to the power FET and thermally coupled thereto. The thermosensitive element is configured to cause the power FET to reduce the load current in case of an exceedance of a limit temperature of the power FET, by interconnecting the gate and first terminal.


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