The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 2022
Filed:
May. 23, 2017
Intel Corporation, Santa Clara, CA (US);
Srinivas V. Pietambaram, Chandler, AZ (US);
Rahul N. Manepalli, Chandler, AZ (US);
David Unruh, Chandler, AZ (US);
Frank Truong, Gilbert, AZ (US);
Kyu Oh Lee, Chandler, AZ (US);
Junnan Zhao, Gilbert, AZ (US);
Sri Chaitra Jyotsna Chavali, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Disclosed herein are integrated circuit (IC) package substrates formed with a dielectric bi-layer, and related devices and methods. In some embodiments, an IC package substrate is fabricated by: forming a raised feature on a conductive layer; forming a dielectric bi-layer on the conductive layer, where the dielectric bi-layer includes a first sub-layer having a first material property and a second sub-layer having a second material property, and where the top surface of the second sub-layer is substantially planar with the top surface of the raised feature; and removing the first sub-layer until the second material property is detected to reveal the conductive feature. In some embodiments, an IC package substrate is fabricated by: forming a dielectric bi-layer on a patterned conductive layer, where the first sub-layer is less susceptible to removal than the second sub-layer; forming an opening in the dielectric bi-layer; etching; and forming a via having vertical sidewalls.