The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2022
Filed:
Jul. 31, 2019
Intel Corporation, Santa Clara, CA (US);
Aleksandar Aleksov, Chandler, AZ (US);
Hiroki Tanaka, Chandler, AZ (US);
Robert A. May, Chandler, AZ (US);
Kristof Darmawikarta, Chandler, AZ (US);
Changhua Liu, Chandler, AZ (US);
Chung Kwang Tan, Chandler, AZ (US);
Srinivas Pietambaram, Gilbert, AZ (US);
Sri Ranga Sai Boyapati, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.