The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2022
Filed:
Mar. 23, 2020
Intel Corporation, Santa Clara, CA (US);
Abhishek Sharma, Hillsboro, OR (US);
Noriyuki Sato, Hillsboro, OR (US);
Sarah Atanasov, Beaverton, OR (US);
Huseyin Ekin Sumbul, Portland, OR (US);
Gregory K. Chen, Portland, OR (US);
Phil Knag, Hillsboro, OR (US);
Ram Krishnamurthy, Portland, OR (US);
Hui Jae Yoo, Hillsboro, OR (US);
Van H. Le, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.