The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2022

Filed:

Dec. 27, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sai Vadlamani, Chandler, AZ (US);

Prithwish Chatterjee, Tempe, AZ (US);

Robert A. May, Chandler, AZ (US);

Rahul S. Jain, Chandler, AZ (US);

Lauren A. Link, Chandler, AZ (US);

Andrew J. Brown, Chandler, AZ (US);

Kyu Oh Lee, Chandler, AZ (US);

Sheng C. Li, Gilbert, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01F 17/00 (2006.01); H01F 41/04 (2006.01); H05K 1/00 (2006.01); H01L 23/00 (2006.01); H01F 27/28 (2006.01); H01F 27/40 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01F 17/0013 (2013.01); H01F 17/0033 (2013.01); H01F 27/2804 (2013.01); H01F 27/40 (2013.01); H01F 41/043 (2013.01); H01F 41/046 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 23/498 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/49866 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H05K 1/00 (2013.01); H01F 2017/0066 (2013.01); H01F 2027/2809 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 24/81 (2013.01); H01L 2224/16157 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81193 (2013.01); H01L 2224/81447 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19102 (2013.01);
Abstract

Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.


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