The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 2021

Filed:

Jan. 14, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Shahab Siddiqui, Clifton Park, NY (US);

Koji Watanabe, Rensselaer, NY (US);

Charlotte DeWan Adams, Schenectady, NY (US);

Kai Zhao, Albany, NY (US);

Daniel James Dechene, Watervliet, NY (US);

Rishikesh Krishnan, Cohoes, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 21/8234 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6675 (2013.01); H01L 21/0259 (2013.01); H01L 21/823431 (2013.01); H01L 29/41733 (2013.01); H01L 29/42384 (2013.01); H01L 29/7869 (2013.01);
Abstract

A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.


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