The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2021

Filed:

Jul. 06, 2018
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Woochan Kim, Sunnyvale, CA (US);

Masamitsu Matsuura, Oita, JP;

Mutsumi Masumoto, Oita, JP;

Kengo Aoya, Oita, JP;

Hau Thanh Nguyen, San Jose, CA (US);

Vivek Kishorechand Arora, San Jose, CA (US);

Anindya Poddar, Sunnyvale, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 23/532 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 23/29 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 23/538 (2006.01); H01L 23/433 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01L 24/24 (2013.01); H01L 21/565 (2013.01); H01L 23/295 (2013.01); H01L 23/3107 (2013.01); H01L 23/3121 (2013.01); H01L 23/4334 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5389 (2013.01); H01L 23/53228 (2013.01); H01L 23/53242 (2013.01); H01L 24/05 (2013.01); H01L 24/19 (2013.01); H01L 24/25 (2013.01); H01L 24/82 (2013.01); H01L 24/96 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 23/367 (2013.01); H01L 23/3675 (2013.01); H01L 23/3677 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/215 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/2518 (2013.01); H01L 2224/821 (2013.01);
Abstract

An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space.


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