The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2021

Filed:

May. 18, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rishabh Mehandru, Portland, OR (US);

Anupama Bowonder, Portland, OR (US);

Biswajeet Guha, Hillsboro, OR (US);

Tahir Ghani, Portland, OR (US);

Stephen M. Cea, Hillsboro, OR (US);

William Hsu, Hillsboro, OR (US);

Szuya S Liao, Portland, OR (US);

Pratik A. Patel, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0646 (2013.01); H01L 29/0615 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

A semiconductor device is described that includes a first semiconductor layer conformally disposed on at least a portion of a source region and a second semiconductor layer conformally disposed on at least a portion of a drain region between the source/drain regions and corresponding gate spacers. The semiconductor layer can prevent diffusion and/or segregation of dopants from the source and drain regions into the gate spacers of the gate stack. Maintaining the intended location of dopant atoms in the source region and drain region improves the electrical characteristics of the semiconductor device including the external resistance ('R') of the semiconductor device.


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