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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11145541 B1

PDFFull Text
Date of Patent:
Oct. 12, 2021

Filed:

Sep. 30, 2017

Conductive via and metal line end fabrication and structures resulting therefrom

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Charles H. Wallace, Portland, OR (US);

Reken Patel, Portland, OR (US);

Hyunsoo Park, Portland, OR (US);

Mohit K. Haran, Hillsboro, OR (US);

Debashish Basu, Beaverton, OR (US);

Curtis W. Ward, Hillsboro, OR (US);

Ruth A. Brain, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Schwabe, Williamson & Wyatt, P.C.

Primary Examiner:

Bradley Smith

Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76831 (2013.01); H01L 21/31116 (2013.01); H01L 21/7684 (2013.01); H01L 21/76816 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01);
Abstract

Conductive via and metal line end fabrication is described. In an example, an interconnect structure includes a first inter-layer dielectric (ILD) on a hardmask layer, where the ILD includes a first ILD opening and a second ILD opening. The interconnect structure further includes an etch stop layer (ESL) on the ILD layer, where the ESL includes a first ESL opening aligned with the first ILD opening to form a first via opening, and where the ESL layer includes a second ESL opening aligned with the second ILD opening. The interconnect structure further includes a first via in the first via opening, a second ILD layer on the first ESL, and a metal line in the second ILD layer, where the metal line is in contact with the first via, and where the metal line includes a first metal opening, and where the metal line includes a second metal opening aligned with the second ILD opening and the ESL opening to form a second via opening. The interconnect structure further includes a metal line end in the first metal opening and further includes a second via in the metal line, where the second via is in the second via opening.

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