The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 2021

Filed:

Jan. 30, 2020
Applicant:

Globalfoundries U.s. Inc., Santa Clara, CA (US);

Inventors:

Heng Yang, Rexford, NY (US);

David Pritchard, Glenville, NY (US);

Kai Sun, Clifton Park, NY (US);

Hongru Ren, Mechanicville, NY (US);

Neha Nayyar, Clifton Park, NY (US);

Manjunatha Prabhu, Clifton Park, NY (US);

Elizabeth Strehlow, Malta, NY (US);

Salvatore Cimino, Waterford, NY (US);

Assignee:

GLOBALFOUNDRIES U.S. INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/47 (2006.01); H01L 29/417 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41741 (2013.01); H01L 29/0847 (2013.01); H01L 29/16 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract

One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.


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