The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 10, 2021
Filed:
Nov. 15, 2019
Applicant:
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Inventors:
Yung-Lung Lin, Taichung, TW;
Hau-Yi Hsiao, Chiayi, TW;
Chih-Hui Huang, Tainan County, TW;
Kuo-Hwa Tzeng, Taipei, TW;
Cheng-Hsien Chou, Tainan, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 21/306 (2006.01); H01L 21/20 (2006.01); H01L 21/18 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02035 (2013.01); H01L 21/02052 (2013.01); H01L 21/02532 (2013.01); H01L 21/30625 (2013.01); H01L 21/76251 (2013.01);
Abstract
The present disclosure provides a method for wafer bonding, including providing a wafer, forming a sacrificial layer on a top surface of the first wafer, trimming an edge of the first wafer to obtain a first wafer area, cleaning the top surface of the first wafer, removing the sacrificial layer, and bonding the top surface of the first wafer to a second wafer having a second wafer area greater than the first wafer area.