The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2021

Filed:

Jun. 30, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Karthik Jambunathan, Hillsboro, OR (US);

Cory C. Bomberger, Portland, OR (US);

Glenn A. Glass, Portland, OR (US);

Anand S. Murthy, Portland, OR (US);

Ju H. Nam, Hillsboro, OR (US);

Tahir Ghani, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7849 (2013.01); H01L 27/0924 (2013.01);
Abstract

An integrated circuit (IC) includes a substrate that includes silicon. A first layer is on the substrate and includes a first monocrystalline semiconductor material, the first layer having a plurality of defects. A second layer is on the first layer and includes a second monocrystalline semiconductor material that includes germanium. A strained channel structure is above the first layer. A gate structure is at least above the channel structure. A source region is adjacent the channel structure. A drain region is adjacent the channel structure, such that the channel structure is laterally between the source region and the drain region.


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