The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

Feb. 21, 2020
Applicant:

Tessera, Inc., San Jose, CA (US);

Inventors:

Marc A. Bergendahl, Troy, NY (US);

Kangguo Cheng, Scheneclady, NY (US);

Fee Li Lie, Albany, NY (US);

Eric R. Miller, Scheneclady, NY (US);

John R. Sporre, Albany, NY (US);

Sean Teehan, Rensselaer, NY (US);

Assignee:

Tessera, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 21/762 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01); H01L 21/311 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6681 (2013.01); H01L 21/31111 (2013.01); H01L 21/76224 (2013.01); H01L 29/0653 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/41725 (2013.01); H01L 29/42392 (2013.01); H01L 29/6653 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/775 (2013.01); H01L 29/7853 (2013.01); H01L 29/78696 (2013.01); H05K 999/99 (2013.01);
Abstract

A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.


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