The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 2021
Filed:
Oct. 21, 2019
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Pin-Dai Sue, Tainan, TW;
Chin-Chou Liu, Jhubei, TW;
Sheng-Hsiung Chen, Zhubei, TW;
Fong-Yuan Chang, Hsinchu, TW;
Lee-Chung Lu, Taipei, TW;
Yen-Hung Lin, Hsinchu, TW;
Li-Chun Tien, Tainan, TW;
Po-Hsiang Huang, Tainan, TW;
Yi-Kan Cheng, Taipei, TW;
Chi-Yu Lu, New Taipei, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Abstract
A method (of generating a layout diagram) includes generating a cell, representing at least part of a circuit in a semiconductor device, which is arranged at least in part according to second tracks of the M_2nd level (M_2nd tracks), and first tracks of the M_1st level (M_1st tracks). The generating the cell includes: selecting, based on a chosen site for the cell in the layout diagram, one of the M_2nd tracks; generating a first M_2nd pin pattern representing an output pin of the circuit; arranging a long axis of the first pin pattern substantially along the selected M_2nd track; generating second, third, fourth and fifth M_1st pin patterns representing corresponding input pins of the circuit; and arranging long axes of the second to fifth pin patterns substantially along corresponding ones of the M_1st tracks.