The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2021

Filed:

Sep. 05, 2019
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Soo Doo Chae, Guilderland, NY (US);

Jeffrey Smith, Clifton Park, NY (US);

Gerrit J. Leusink, Rexford, NY (US);

Robert D. Clark, Livermore, NY (US);

Kai-Hung Yu, Watervliet, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76835 (2013.01); H01L 21/76808 (2013.01); H01L 21/76811 (2013.01); H01L 21/76813 (2013.01); H01L 21/76816 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 21/76877 (2013.01); H01L 23/522 (2013.01); H01L 23/53228 (2013.01); H01L 23/53257 (2013.01); H01L 21/28562 (2013.01); H01L 21/76883 (2013.01); H01L 2221/1031 (2013.01);
Abstract

A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.


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