The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 2020
Filed:
Sep. 25, 2015
Intel Corporation, Santa Clara, CA (US);
Glenn A. Glass, Portland, OR (US);
Prashant Majhi, San Jose, CA (US);
Anand S. Murthy, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Daniel B. Aubertine, North Plains, OR (US);
Heidi M. Meyer, Hillsboro, OR (US);
Karthik Jambunathan, Hillsboro, OR (US);
Gopinath Bhimarasetti, Portland, OR (US);
INTEL Corporation, Santa Clara, CA (US);
Abstract
Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.