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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10861744 B1

PDFFull Text
Date of Patent:
Dec. 08, 2020

Filed:

Mar. 18, 2019

Platform and method of operating for integrated end-to-end cmp-less interconnect process

Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Ying Trickett, Albany, NY (US);

Kai-Hung Yu, Albany, NY (US);

Nicholas Joy, Albany, NY (US);

Kaoru Maekawa, Albany, NY (US);

Robert Clark, Albany, NY (US);

Assignee:

Tokyo Electron Limited, Tokyo, JP;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Caridad Everhart

Assistant Examiner:

Ankush K Singal

Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/768 (2006.01); H01L 21/67 (2006.01); H01L 21/66 (2006.01); H01L 21/677 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/311 (2006.01); G05B 13/02 (2006.01); G05B 19/418 (2006.01); C23C 14/24 (2006.01); C23C 14/34 (2006.01); H01J 37/32 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76879 (2013.01); G05B 13/027 (2013.01); G05B 19/41875 (2013.01); H01L 21/0228 (2013.01); H01L 21/02271 (2013.01); H01L 21/28562 (2013.01); H01L 21/31116 (2013.01); H01L 21/67023 (2013.01); H01L 21/67063 (2013.01); H01L 21/67161 (2013.01); H01L 21/67167 (2013.01); H01L 21/67184 (2013.01); H01L 21/67196 (2013.01); H01L 21/67225 (2013.01); H01L 21/67253 (2013.01); H01L 21/67276 (2013.01); H01L 21/67288 (2013.01); H01L 21/67703 (2013.01); H01L 21/67742 (2013.01); H01L 21/67745 (2013.01); H01L 21/7685 (2013.01); H01L 21/76802 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 21/76897 (2013.01); H01L 22/12 (2013.01); C23C 14/24 (2013.01); C23C 14/34 (2013.01); G05B 2219/32368 (2013.01); G05B 2219/45031 (2013.01); H01J 37/32 (2013.01); H01L 21/67017 (2013.01); H01L 21/67207 (2013.01);
Abstract

A method of processing materials on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules is provided. A workpiece having an upper planar surface is received into the common manufacturing platform. The method further includes conformally applying a thin film over the feature pattern using one of the film-forming modules, removing the thin film from upper surfaces of the feature pattern using one of the etching modules to leave behind the thin film in the recessed feature, and removing the fill material from the upper planar surface of the workpiece. The integrated sequence of processing steps is executed in a controlled environment within the common manufacturing platform and without leaving the controlled environment.

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