The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2020
Filed:
Dec. 13, 2016
Intel Corporation, Santa Clara, CA (US);
Rahul Ramaswamy, Portland, OR (US);
Hsu-Yu Chang, Hillsboro, OR (US);
Chia-Hong Jan, Portland, OR (US);
Walid M. Hafez, Portland, OR (US);
Neville L. Dias, Hillsboro, OR (US);
Roman W. Olac-Vaw, Hillsboro, OR (US);
Chen-Guan Lee, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A transistor including a channel disposed between a source and a drain, a gate electrode disposed on the channel and surrounding the channel, wherein the source and the drain are formed in a body on a substrate and the channel is separated from the body. A method of forming an integrated circuit device including forming a trench in a dielectric layer on a substrate, the trench including dimensions for a transistor body including a width; forming a channel material in the trench; recessing the dielectric layer to expose a first portion of the channel material; increasing a width dimension of the exposed channel material; recessing the dielectric layer to expose a second portion of the channel material; removing the second portion of the channel material; and forming a gate stack on the first portion of the channel material, the gate stack including a gate dielectric and a gate electrode.