The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2020

Filed:

Jul. 21, 2017
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Jung-Chih Tsao, Tainan, TW;

Chi-Cheng Hung, Tainan, TW;

Yu-Sheng Wang, Tainan, TW;

Wen-Hsi Lee, Kaohsiung, TW;

Kei-Wei Chen, Tainan, TW;

Ying-Lang Wang, Tien-Chung Village, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0653 (2013.01); H01L 21/28088 (2013.01); H01L 29/4966 (2013.01); H01L 29/6656 (2013.01); H01L 29/66553 (2013.01); H01L 29/7834 (2013.01); H01L 29/6659 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01);
Abstract

A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer.


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