The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2020
Filed:
Jul. 02, 2016
Intel Corporation, Santa Clara, CA (US);
Kemal Aygun, Chandler, AZ (US);
Richard J. Dischler, Bolton, MA (US);
Jeff C. Morriss, Cornelius, OR (US);
Zhiguo Qian, Chandler, AZ (US);
Wilfred Gomes, Portland, OR (US);
Yu Amos Zhang, Chandler, AZ (US);
Ram S. Viswanath, Phoenix, AZ (US);
Rajasekaran Swaminathan, Tempe, AZ (US);
Sriram Srinivasan, Chandler, AZ (US);
Yidnekachew S. Mekonnen, Chandler, AZ (US);
Sanka Ganesan, Chandler, AZ (US);
Eduard Roytman, Newton Centre, MA (US);
Mathew J. Manusharow, Phoenix, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.