The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2020
Filed:
Sep. 24, 2015
Intel Corporation, Santa Clara, CA (US);
Sansaptak W. Dasgupta, Hillsboro, CA (US);
Marko Radosavljevic, Portland, OR (US);
Han Wui Then, Portland, OR (US);
Ravi Pillarisetty, Portland, OR (US);
Kimin Jun, Portland, OR (US);
Patrick Morrow, Portland, OR (US);
Valluri R. Rao, Saratoga, CA (US);
Paul B. Fischer, Portland, OR (US);
Robert S. Chau, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
The electrical and electrochemical properties of various semiconductors may limit the usefulness of various semiconductor materials for one or more purposes. A completed gallium nitride (GaN) semiconductor layer containing a number of GaN power management integrated circuit (PMIC) dies may be bonded to a completed silicon semiconductor layer containing a number of complementary metal oxide (CMOS) control circuit dies. The completed GaN layer and the completed silicon layer may be full size (e.g., 300 mm). A layer transfer operation may be used to bond the completed GaN layer to the completed silicon layer. The layer transfer operation may be performed on full size wafers. After slicing the full size wafers a large number of multi-layer dies, each having a GaN die layer transferred to a silicon die may be produced.