The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2020
Filed:
Aug. 19, 2014
Intel Corporation, Santa Clara, CA (US);
Roman Olac-Vaw, Hillsboro, OR (US);
Walid Hafez, Portland, OR (US);
Chia-Hong Jan, Portland, OR (US);
Hsu-Yu Chang, Hillsboro, OR (US);
Ting Chang, Portland, OR (US);
Rahul Ramaswamy, Hillsboro, OR (US);
Pei-Chi Liu, Portland, OR (US);
Neville Dias, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.