The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2020
Filed:
Mar. 10, 2016
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Gilbert Dewey, Hillsboro, OR (US);
Mark L. Doczy, Portland, OR (US);
Suman Datta, Beaverton, OR (US);
Justin K. Brask, Portland, OR (US);
Matthew V. Metz, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/513 (2013.01); H01L 21/28088 (2013.01); H01L 21/28194 (2013.01); H01L 21/823437 (2013.01); H01L 21/823462 (2013.01); H01L 21/823828 (2013.01); H01L 21/823857 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/78 (2013.01); H01L 29/665 (2013.01); H01L 29/6659 (2013.01); H01L 29/66795 (2013.01);
Abstract
A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. The method includes depositing a dielectric layer on a substrate, followed by deposition of a capping layer in-situ over the dielectric layer prior to any high temperature processing.