The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Apr. 27, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Min-Hsiu Hung, Tainan, TW;

Yi-Hsiang Chao, New Taipei, TW;

Kuan-Yu Yeh, Taoyuan, TW;

Kan-Ju Lin, Kaohsiung, TW;

Chun-Wen Nieh, Zhubei, TW;

Huang-Yi Huang, Hsinchu, TW;

Chih-Wei Chang, Hsinchu, TW;

Ching-Hwanq Su, Tainan, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/45 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 21/3213 (2006.01); H01L 21/3205 (2006.01); H01L 21/321 (2006.01); H01L 21/306 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/45 (2013.01); H01L 21/321 (2013.01); H01L 21/32053 (2013.01); H01L 21/32135 (2013.01); H01L 21/32136 (2013.01); H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 21/76856 (2013.01); H01L 21/76865 (2013.01); H01L 21/76877 (2013.01); H01L 21/76889 (2013.01); H01L 21/76897 (2013.01); H01L 29/41791 (2013.01); H01L 29/665 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 21/30604 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01); H01L 29/0847 (2013.01); H01L 29/41783 (2013.01); H01L 29/66636 (2013.01); H01L 29/7848 (2013.01);
Abstract

A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate including a conductive region made of silicon, germanium or a combination thereof. The method also includes forming an insulating layer over the semiconductor substrate and forming an opening in the insulating layer to expose the conductive region. The method also includes performing a deposition process to form a metal layer over a sidewall and a bottom of the opening, so that a metal silicide or germanide layer is formed on the exposed conductive region by the deposition process. The method also includes performing a first in-situ etching process to etch at least a portion of the metal layer and forming a fill metal material layer in the opening.


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