The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Nov. 06, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yu-Ching Lee, Kaohsiung, TW;

Ching-Fang Yu, Hsinchu, TW;

Chun-Hung Lin, Taoyuan, TW;

Ting-Hao Hsu, Hsinchu, TW;

Ching-Hsiang Chang, Taipei, TW;

Sheng-Chi Chin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 1/64 (2012.01); G03F 7/20 (2006.01);
U.S. Cl.
CPC ...
G03F 1/64 (2013.01); G03F 7/2004 (2013.01);
Abstract

Pellicle-mask systems for advanced lithography, such as extreme ultraviolet lithography, are disclosed herein. An exemplary pellicle-mask system includes a mask having an integrated circuit (IC) pattern, a pellicle membrane, and a pellicle frame. The pellicle frame has a first surface attached to the pellicle membrane and a second surface opposite the first surface attached to the mask, such that the IC pattern of the mask is positioned within an enclosed space defined by the mask, the pellicle membrane, and the pellicle frame. A void is defined between the pellicle frame and the mask, where the void is defined by a portion of the second surface of the pellicle membrane not attached to the mask. The void is not in communication with the enclosed space and is not in communication with an exterior space of the pellicle-mask system.


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