The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2020
Filed:
Aug. 24, 2018
Micron Technology, Inc., Boise, ID (US);
Collin Howder, Meridian, ID (US);
Justin B. Dorhout, Boise, ID (US);
Anish A. Khandekar, Boise, ID (US);
Mark W. Kiehlbauch, Boise, ID (US);
Nancy M. Lomeli, Boise, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
A method of forming an array of elevationally-extending strings of memory cells comprises forming and removing a portion of lower-stack memory cell material that is laterally across individual bases in individual lower channel openings. Covering material is formed in a lowest portion of the individual lower channel openings to cover the individual bases of the individual lower channel openings. Upper channel openings are formed into an upper stack to the lower channel openings to form interconnected channel openings individually comprising one of the individual lower channel openings and individual of the upper channel openings. A portion of upper-stack memory cell material that is laterally across individual bases in individual upper channel openings is formed and removed. After the removing of the portion of the upper-stack memory cell material, the covering material is removed from the interconnected channel openings. After the removing of the covering material, transistor channel material is formed in an upper portion of the interconnected channel openings. After forming the transistor channel material, upper-stack and lower-stack sacrificial material is replaced with control-gate material having terminal ends corresponding to control-gate regions of individual memory cells. Charge-storage material is formed between the transistor channel material and the control-gate regions. Insulative charge-passage material is formed between the transistor channel material and the charge-storage material. A charge-blocking region is between the charge-storage material and individual of the control-gate regions.