The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2019
Filed:
Nov. 06, 2017
Applied Materials, Inc., Santa Clara, CA (US);
Shiyu Sun, Santa Clara, CA (US);
Nam Sung Kim, Sunnyvale, CA (US);
Naomi Yoshida, Sunnyvale, CA (US);
Theresa Kramer Guarini, San Jose, CA (US);
Sung Won Jun, San Jose, CA (US);
Vanessa Pena, Heverlee, BE;
Errol Antonio C. Sanchez, Tracy, CA (US);
Benjamin Colombeau, Salem, MA (US);
Michael Chudzik, Mountain View, CA (US);
Bingxi Wood, Cupertino, CA (US);
APPLIED MATERIALS, INC., Santa Clara, CA (US);
Abstract
Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.