The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

Feb. 04, 2019
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Michael Wenyoung Tsiang, Fremont, CA (US);

Praket P. Jha, San Jose, CA (US);

Xinhai Han, Santa Clara, CA (US);

Bok Hoen Kim, San Jose, CA (US);

Sang Hyuk Kim, Gyeonggi, KR;

Myung Hun Ju, Gyeonggi-do, KR;

Hyung Jin Park, Icheon, KR;

Ryeun Kwan Kim, Wonju-Si, KR;

Jin Chul Son, Hwa Sung-Si, KR;

Saiprasanna Gnanavelu, Santa Clara, CA (US);

Mayur G. Kulkarni, Sunnyvale, CA (US);

Sanjeev Baluja, Campbell, CA (US);

Majid K. Shahreza, San Jose, CA (US);

Jason K. Foster, San Jose, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); C23C 16/02 (2006.01); C23C 16/505 (2006.01); C23C 16/52 (2006.01); C23C 16/40 (2006.01); H01L 27/11582 (2017.01); H01L 29/06 (2006.01); H01L 21/3115 (2006.01); H01L 27/11556 (2017.01); H01L 27/11575 (2017.01); H01L 27/11548 (2017.01); H01L 21/768 (2006.01); C23C 16/455 (2006.01); H01L 21/311 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); C23C 16/0272 (2013.01); C23C 16/402 (2013.01); C23C 16/45523 (2013.01); C23C 16/505 (2013.01); C23C 16/52 (2013.01); H01L 21/022 (2013.01); H01L 21/02164 (2013.01); H01L 21/02211 (2013.01); H01L 21/02216 (2013.01); H01L 21/02274 (2013.01); H01L 21/02304 (2013.01); H01L 21/02321 (2013.01); H01L 21/02337 (2013.01); H01L 21/3115 (2013.01); H01L 21/76801 (2013.01); H01L 27/11548 (2013.01); H01L 27/11556 (2013.01); H01L 27/11575 (2013.01); H01L 29/06 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01);
Abstract

Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.


Find Patent Forward Citations

Loading…