The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2019

Filed:

Oct. 09, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Haiting Wang, Clifton Park, NY (US);

Wei Zhao, Fort Lee, NJ (US);

Hui Zang, Guilderland, NY (US);

Hong Yu, Rexford, NY (US);

Zhenyu Hu, Clifton Park, NY (US);

Scott Beasor, Greenwich, NY (US);

Erik Geiss, Mechanicville, NY (US);

Jerome Ciavatti, Mechanicville, NY (US);

Jae Gon Lee, Waterford, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 27/11 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41791 (2013.01); H01L 21/823431 (2013.01); H01L 21/823821 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 27/1104 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.


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