The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2019
Filed:
Feb. 10, 2017
Intel Corporation, Santa Clara, CA (US);
Niti Goel, Portland, OR (US);
Benjamin Chu-Kung, Portland, OR (US);
Sansaptak Dasgupta, Hillsboro, OR (US);
Niloy Mukherjee, Portland, OR (US);
Matthew V. Metz, Portland, OR (US);
Van H. Le, Portland, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Robert S. Chau, Beaverton, OR (US);
Ravi Pillarisetty, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystaline defects in the fins due to lattice mismatch in the layer interfaces.