The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

Jan. 26, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tsung-Fu Tsai, Changhua, TW;

Chia-Wei Tu, Chunan Town, TW;

Yian-Liang Kuo, Hsinchu, TW;

Ru-Ying Huang, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/58 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 24/14 (2013.01); H01L 23/562 (2013.01); H01L 23/585 (2013.01); H01L 25/0657 (2013.01); H01L 23/522 (2013.01); H01L 24/13 (2013.01); H01L 2224/10126 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13644 (2013.01); H01L 2224/13655 (2013.01); H01L 2224/13664 (2013.01); H01L 2224/17517 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06544 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/3512 (2013.01);
Abstract

A chip includes a first group of dummy bumps disposed at a top surface of the chip in a first corner of the chip, a second group of dummy bumps disposed at the top surface of the chip in a second corner of the chip, and active bump connectors disposed at the top surface of the chip. The chip also includes an outer seal ring disposed around a periphery of the chip, a first seal ring arrangement disposed around the first group of dummy bumps, and a second seal ring arrangement disposed around the second group of dummy bumps. The first seal ring arrangement and second seal ring arrangement are disposed in dielectric layers underlying the first and second groups of dummy bumps.


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