The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Aug. 24, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Collin Howder, Meridian, ID (US);

Justin B. Dorhout, Boise, ID (US);

Anish A. Khandekar, Boise, ID (US);

Mark W. Kiehlbauch, Boise, ID (US);

Nancy M. Lomeli, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11521 (2017.01); H01L 27/11556 (2017.01); H01L 21/02 (2006.01); H01L 27/11568 (2017.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/02532 (2013.01); H01L 21/02645 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 27/11521 (2013.01); H01L 27/11556 (2013.01); H01L 27/11568 (2013.01);
Abstract

A method used in forming an array of elevationally-extending strings of memory cells comprises forming a lower stack comprising vertically-alternating insulative tiers and wordline tiers. Lower channel openings are in the lower stack. A bridge is epitaxially grown that covers individual of the lower channel openings. A lower void space is beneath individual of the bridges in the individual lower channel openings. An upper stack is formed above the lower stack. The upper stack comprises vertically-alternating insulative tiers and wordline tiers. Upper channel openings are formed into the upper stack to the individual bridges to form interconnected channel openings individually comprising one of the individual lower channel openings and individual of the upper channel openings. The interconnected channel openings individually have one of the individual bridges there-across. The individual bridges are penetrated through to uncover individual of the lower void spaces. Transistor channel material is formed in an upper portion of the interconnected channel openings elevationally along the vertically-alternating tiers in the upper stack.


Find Patent Forward Citations

Howder, Collin. (2019). Methods used in forming an array of elevationally-extending strings of memory cells, methods of forming an array of elevationally-extending strings of memory cells, and methods of forming an array of vertical strings of memory cells (U.S. Patent No. 10446578). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10446578

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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