The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2019
Filed:
Jun. 21, 2018
Intel Corporation, Santa Clara, CA (US);
Srinivas Pietambaram, Chandler, AZ (US);
Jung Kyu Han, Chandler, AZ (US);
Ali Lehaf, Chandler, AZ (US);
Steve Cho, Chandler, AZ (US);
Thomas Heaton, Mesa, AZ (US);
Hiroki Tanaka, Chandler, AZ (US);
Kristof Darmawikarta, Chandler, AZ (US);
Robert Alan May, Chandler, AZ (US);
Sri Ranga Sai Boyapati, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.