The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Jan. 03, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Hui Zang, Guilderland, NY (US);

Jianwei Peng, Latham, NY (US);

Yi Qi, Niskayuna, NY (US);

Hsien-Ching Lo, Guilderland, NY (US);

Jerome Ciavatti, Mechanicville, NY (US);

Ruilong Xie, Schenectady, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8234 (2006.01); H01L 29/08 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823487 (2013.01); H01L 21/2018 (2013.01); H01L 21/823418 (2013.01); H01L 21/823456 (2013.01); H01L 27/088 (2013.01); H01L 29/0847 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.


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