The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2019
Filed:
Sep. 22, 2016
Pdf Solutions, Inc., San Jose, CA (US);
Yih-Yuh Doong, Zhubei, TW;
Sheng-Che Lin, Baoshan Township, TW;
Chia-Chi Lin, Hsinchu, TW;
Hans Eisenmann, Tutzing, DE;
Cho-Si Huang, Baoshan Township, TW;
Tzupin Shen, Hsinchu, TW;
Christopher Hess, Belmont, CA (US);
Kimon Michaels, Monte Sereno, CA (US);
PDF Solutions, Inc., San Jose, CA (US);
Abstract
A method is disclosed for designing a test vehicle utilizing a layout of a real integrated circuit (IC) product. The method comprises: importing an original full-chip layout of the real IC product; partitioning the original full-chip layout into probe groups, each probe group comprising probe pads, and, a plurality of IC devices within an area of interest (AOI) having original routing interconnect for those IC devices; selecting a set of IC devices within the AOI; and, for the selected set of IC devices, using pattern extraction to remove the original routing interconnect, and create customized interconnect layers (CIL) to reconfigure connection between the individual IC devices. Incorporating the selected set of IC devices with the CIL into the original full-chip layout creates a modified full-chip layout such that a wafer fabricated using the modified full-chip layout comprises a real product with a built-in test vehicle.