The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

Jan. 15, 2017
Applicant:

Kla-tencor Corporation, Milpitas, CA (US);

Inventors:

Haiguang Chen, Mounatin View, CA (US);

Jaydeep Sinha, Livermore, CA (US);

Sergey Kamensky, Campbell, CA (US);

Sathish Veeraraghavan, Santa Clara, CA (US);

Pradeep Vukkadala, Newark, CA (US);

Assignee:

KLA-Tencor Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01N 21/95 (2006.01); G01B 11/24 (2006.01); G06T 7/00 (2017.01); G06T 7/60 (2017.01); G06K 9/62 (2006.01);
U.S. Cl.
CPC ...
G01N 21/9501 (2013.01); G01B 11/24 (2013.01); G06K 9/6267 (2013.01); G06T 7/0004 (2013.01); G06T 7/60 (2013.01); G06T 2207/20021 (2013.01); G06T 2207/30148 (2013.01);
Abstract

Systems and methods for improving results of wafer higher order shape (HOS) characterization and wafer classification are disclosed. The systems and methods in accordance with the present disclosure are based on localized shapes. A wafer map is partitioned into a plurality of measurement sites to improve the completeness of wafer shape representation. Various site based HOS metric values may be calculated for wafer characterization and/or classification purposes, and may also be utilized as control input for a downstream application. In addition, polar grid partitioning schemes are provided. Such polar grid partitioning schemes may be utilized to partition a wafer surface into measurement sites having uniform site areas while providing good wafer edge region coverage.


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