The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2019

Filed:

Sep. 24, 2015
Applicants:

Intel Corporation, Santa Clara, CA (US);

Patrick Morrow, Portland, OR (US);

Mauro J. Kobrinsky, Portland, OR (US);

Kimin Jun, Portland, OR (US);

Il-seok Son, Portland, OR (US);

Paul B. Fischer, Portland, OR (US);

Inventors:

Patrick Morrow, Portland, OR (US);

Mauro J. Kobrinsky, Portland, OR (US);

Kimin Jun, Portland, OR (US);

Il-Seok Son, Portland, OR (US);

Paul B. Fischer, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/00 (2006.01); H01L 29/00 (2006.01); H01L 29/417 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/088 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41791 (2013.01); H01L 21/02532 (2013.01); H01L 21/76897 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 21/845 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/0886 (2013.01); H01L 27/1211 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/165 (2013.01); H01L 29/41775 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01); H01L 21/02529 (2013.01); H01L 21/26513 (2013.01); H01L 21/30604 (2013.01); H01L 21/324 (2013.01); H01L 29/6656 (2013.01);
Abstract

Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.


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