The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Jun. 27, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Neville L. Dias, Hillsboro, OR (US);

Chia-Hong Jan, Portland, OR (US);

Walid M. Hafez, Portland, OR (US);

Roman W. Olac-Vaw, Hillsboro, OR (US);

Hsu-Yu Chang, Hillsboro, OR (US);

Ting Chang, Hillsboro, OR (US);

Rahul Ramaswamy, Hillsboro, OR (US);

Pei-Chi Liu, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H03D 7/14 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H03D 7/16 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7853 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/845 (2013.01); H01L 27/0886 (2013.01); H01L 27/1211 (2013.01); H01L 29/0657 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H03D 7/1425 (2013.01); H03D 7/1441 (2013.01); H03D 7/1458 (2013.01); H03D 7/1466 (2013.01); H03D 7/165 (2013.01); H01L 29/41791 (2013.01);
Abstract

An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.


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