The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Mar. 31, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Seok Ling Lim, Kulim, MY;

Eng Huat Goh, Ayer Itam, MY;

Hoay Tien Teoh, Paya Terubong, MY;

Jenny Shio Yin Ong, Bayan Lepas, MY;

Jia Yan Go, Kulim, MY;

Jiun Hann Sir, Gelugor, MY;

Min Suet Lim, Bayan Lapas, MY;

Assignee:

INTEL CORPORATION, Santa Clara, unknown;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/043 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 23/5222 (2013.01); H01L 23/5286 (2013.01); H01L 23/043 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/1047 (2013.01);
Abstract

Interconnects for semiconductor packages are described. An apparatus may comprise a decoupling capacitor on a logic board, and a conductive interconnect element on the logic board, the conductive interconnect element to connect the decoupling capacitor on the logic board to a power conductor comprising a power pad of a semiconductor package, the conductive interconnect element at a different layer than a ground-potential layer of the logic board. Other embodiments are described and claimed.


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