The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Apr. 04, 2017
Applicant:

Siliconware Precision Industries Co., Ltd., Taichung, TW;

Inventors:

Cheng-Chia Chiang, Taichung, TW;

Don-Son Jiang, Taichung, TW;

Lung-Yuan Wang, Taichung, TW;

Shih-Hao Tung, Taichung, TW;

Shu-Huei Huang, Taichung, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 21/563 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/49811 (2013.01); H01L 23/49816 (2013.01); H01L 23/5389 (2013.01); H01L 24/81 (2013.01); H01L 24/16 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05568 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13023 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/92125 (2013.01); H01L 2924/14 (2013.01); H01L 2924/18161 (2013.01);
Abstract

A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.


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