The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2018

Filed:

Aug. 09, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Li-Ting Wang, Tainan, TW;

Teng-Chun Tsai, Hsin-Chu, TW;

Chun-Hsiung Lin, Zhubei, TW;

Cheng-Tung Lin, Jhudong Township, TW;

Chi-Yuan Chen, Taichung, TW;

Hong-Mao Lee, Hsin-Chu, TW;

Huicheng Chang, Tainan, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/225 (2006.01); H01L 21/285 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/665 (2013.01); H01L 21/2254 (2013.01); H01L 21/28518 (2013.01); H01L 21/76224 (2013.01); H01L 29/1054 (2013.01); H01L 29/6659 (2013.01); H01L 29/66545 (2013.01); H01L 29/66651 (2013.01); H01L 29/66803 (2013.01);
Abstract

A method includes forming a gate stack over a semiconductor region, depositing an impurity layer over the semiconductor region, and depositing a metal layer over the impurity layer. An annealing is then performed, wherein the elements in the impurity layer are diffused into a portion of the semiconductor region by the annealing to form a source/drain region, and wherein the metal layer reacts with a surface layer of the portion of the semiconductor region to form a source/drain silicide region over the source/drain region.


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