The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2018
Filed:
Mar. 16, 2017
Applicant:
Xintec Inc., Taoyuan, TW;
Inventors:
Yen-Shih Ho, Kaohsiung, TW;
Chia-Sheng Lin, Taoyuan, TW;
Po-Han Lee, Taipei, TW;
Wei-Luen Suen, New Taipei, TW;
Assignee:
XINTEC INC., Taoyuan, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/544 (2006.01); H01L 23/58 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 23/3114 (2013.01); H01L 23/544 (2013.01); H01L 23/585 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2223/5446 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05008 (2013.01); H01L 2224/13024 (2013.01);
Abstract
A chip package including a substrate that has a first surface and a second surface opposite thereto is provided. The substrate includes a chip region and a scribe line region that extends along the edge of the chip region. The chip package further includes a dielectric layer disposed on the first surface of the substrate. The dielectric layer corresponding to the scribe line region has a through groove that extends along the extending direction of the scribe line region. A method of forming the chip package is also provided.