The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

May. 18, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Hsien-Liang Meng, Hsin-Chu, TW;

Wei-Hung Lin, Xinfeng Township, TW;

Yu-min Liang, Zhongli, TW;

Ming-Che Ho, Tainan, TW;

Hung-Jui Kuo, Hsin-Chu, TW;

Chung-Shi Liu, Hsin-Chu, TW;

Mirng-Ji Lii, Sinpu Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/561 (2013.01); H01L 21/563 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 21/7806 (2013.01); H01L 23/3128 (2013.01); H01L 23/49811 (2013.01); H01L 23/5383 (2013.01); H01L 23/562 (2013.01); H01L 23/49816 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/92 (2013.01); H01L 25/18 (2013.01); H01L 2221/68345 (2013.01); H01L 2224/13101 (2013.01); H01L 2224/13124 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/13184 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/81805 (2013.01); H01L 2224/92125 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/18161 (2013.01);
Abstract

A packaging structure and a method of forming a packaging structure are provided. The packaging structure, such as an interposer, is formed by optionally bonding two carrier substrates together and simultaneously processing two carrier substrates. The processing includes forming a sacrificial layer over the carrier substrates. Openings are formed in the sacrificial layers and pillars are formed in the openings. Substrates are attached to the sacrificial layer. Redistribution lines may be formed on an opposing side of the substrates and vias may be formed to provide electrical contacts to the pillars. A debond process may be performed to separate the carrier substrates. Integrated circuit dies may be attached to one side of the redistribution lines and the sacrificial layer is removed.


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