The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2018

Filed:

Jun. 03, 2016
Applicant:

Kla-tencor Corporation, Milpitas, CA (US);

Inventors:

Pradeep Vukkadala, Newark, CA (US);

Sathish Veeraraghavan, Santa Clara, CA (US);

Jaydeep Sinha, Livermore, CA (US);

Haiguang Chen, Mountain View, CA (US);

Michael Kirk, Los Altos Hills, CA (US);

Assignee:

KLA-Tencor Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06G 7/48 (2006.01); G06F 17/50 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5018 (2013.01); H01L 21/67288 (2013.01);
Abstract

Systems and methods for prediction of in-plane distortions (IPD) due to wafer shape in semiconductor wafer chucking process is disclosed. A series of Zernike basis wafer shapes process to emulate the non-linear finite element (FE) contact mechanics model based IPD prediction is utilized in accordance with one embodiment of the present disclosure. The emulated FE model based prediction process is substantially more efficient and provides accuracy comparable to the FE model based IPD prediction that utilizes full-scale 3-D wafer and chuck geometry information and requires computation intensive simulations. Furthermore, an enhanced HOS IPD/OPD prediction process based on a series of Zernike basis wafer shape images is also disclosed.


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