Taichung, Taiwan

Zhen-Cheng Chou

This inventor holds 1 USPTO granted patent. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2005.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Zhen-Cheng Chou. Retrieved from https://idiyas.com/inventor/zhen-cheng-chou

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 4.0

ph-index = 1


Company Filing History:


Years Active: 2005

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1 patent (USPTO):Explore Patents

Title: Zhen-Cheng Chou and His Microelectronic Fabrication Patent

Introduction

Zhen-Cheng Chou is an inventor associated with Taichung, Taiwan, and Taiwan Semiconductor Manufacturing Company Limited. His patent work addresses methods for processing microelectronic layers with improved fabrication reliability.

Latest Patents

Chou is associated with 1 patent: “Partially Photoexposed Positive Photoresist Layer Blocking Method for Regio-Selectively Processing a Microelectronic Layer.” The method uses a patterned positive photoresist residue as a protective layer inside an aperture while an upper region of a topographic microelectronic layer is processed. The residue is formed through incomplete vertical but complete horizontal exposure and development of a positive photoresist layer that fills the aperture. This approach is intended to enhance the reliability of the microelectronic fabrication.

Career Highlights

Chou’s listed patent reflects work on photoresist patterning and selective processing in microelectronic manufacturing. The disclosed method focuses on protecting a region within an aperture during fabrication.

Collaborations

The listed coworkers associated with Chou are Yong-Shun Liao and Juing-Yi Wu.

Conclusion

Zhen-Cheng Chou’s patent describes a photoresist-based protective technique for regio-selective microelectronic processing, with the goal of improving fabrication reliability.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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