Shanghai, China

Yu Yang

USPTO Granted Patents = 3 

Average Co-Inventor Count = 4.5

ph-index = 1


Company Filing History:


Years Active: 2023-2024

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3 patents (USPTO):Explore Patents

Title: Innovations of Yu Yang in Machine Learning and Delay Estimation

Introduction

Yu Yang is an accomplished inventor based in Shanghai, China. He has made significant contributions to the field of electronic design automation, particularly in the area of delay estimation using machine learning techniques. With a total of 3 patents to his name, Yang's work is paving the way for more efficient and accurate electronic designs.

Latest Patents

One of Yu Yang's latest patents is titled "Integrating machine learning delay estimation in FPGA-based emulation systems." This innovative method estimates delays in design under tests (DUTs) by utilizing machine learning. The system accesses multiple DUTs, each comprising various logic blocks. For each DUT, a combinatorial path is identified, connecting one or more logic blocks. A feature vector is generated, including values of orthogonal features representing the combinatorial path's characteristics. Each DUT is compiled for emulation, and the delay of its combinatorial path is measured. These measured delays, along with the corresponding feature vectors, are used to train a machine learning delay model. The trained model is designed to receive a combinatorial path of a DUT as input and generate an estimated wire delay as output. This approach leverages machine learning to predict delays in electronic designs, improving the efficiency and accuracy of delay estimations in complex circuits.

Another notable patent is "Machine learning delay estimation for emulation systems." This delay estimation system estimates a delay of a DUT for an emulation system. The system receives logic blocks of the DUT and a combinatorial path connecting one or more of the logic blocks. It applies a delay model to a feature vector representing the combinatorial path, where the delay model can determine a delay of the combinatorial path. The delay model may be a machine learning model. The system generates a timing graph using the determined delay and provides the timing graph to a compiler to perform placement and routing of the DUT.

Career Highlights

Yu Yang is currently employed at Synopsys, Inc., a leading company in electronic design automation. His work at Synopsys has allowed him to focus on innovative solutions that enhance the performance and reliability of electronic systems.

Collaborations

Throughout his career, Yu Yang has collaborated with talented individuals such as Jianfeng Huang and Yanhua Yi. These collaborations have contributed to the advancement of technology in the field of electronic design.

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