The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

Dec. 10, 2021
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Yanhua Yi, Cupertino, CA (US);

Yu Yang, Shanghai, CN;

Jiajun Fan, Shanghai, CN;

Vinod Kumar Nakkala, San Jose, CA (US);

Vijay Sundaresan, Milpitas, CA (US);

Jianfeng Huang, Shanghai, CN;

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G01R 31/3183 (2006.01); G06F 30/3308 (2020.01); G06F 11/26 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318321 (2013.01); G01R 31/318328 (2013.01); G01R 31/318357 (2013.01); G06F 11/261 (2013.01); G06F 30/3308 (2020.01);
Abstract

A delay estimation system estimates a delay of a DUT for an emulation system. The delay estimation system receives logic blocks of the DUT and a combinatorial path connecting one or more of the logic blocks. The system applies a delay model to a feature vector representing the combinatorial path, where the delay model can determine a delay of the combinatorial path. The delay model may be a machine learning model. The system generates a timing graph using the determined delay and provides the timing graph to a compiler to perform placement and routing of the DUT.


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